This disclosure relates generally to the field of circuitry for determination of the resistance of an array of capacitive elements.
A computer memory, such as dynamic random access memory (DRAM), may include an array of capacitive memory elements. The capacitive memory elements may be deep trench capacitors, and the array of capacitive memory elements may be connected by a single interconnect level. The total series resistance of the array of capacitive memory elements should be reduced in order to reduce the amount of time necessary for read and write operations in the computer memory. However, the resistance of an array of capacitive elements is difficult to measure because the resistance of the capacitive elements is in series with the capacitive elements' capacitance. The resistance of an array of capacitive elements may only be observable using measurements at frequencies near the bandwidth of the capacitive elements, which may be about 1 gigahertz. Such measurements require equipment that may not be available on an in-line parametric tester, such as a 10 gigahertz network analyzer, and may require more than one interconnect level to reduce parasitic capacitance.